The present disclosure relates to testing electronic components, and more specifically, hierarchal test block test pattern reduction in on-product test compression (OPTC) systems.
Digital Integrated Circuits (ICs) can be prone to defects introduced during a manufacturing process. These defects may affect the logic output of the digital IC, which in turn adversely influences semiconductor chip quality and costs. Industry has developed a number of testing techniques to test for the defects. To test for defects, an OPTC network may be built into an IC, allowing the IC to test its own operations. OPTC networks may be implemented using hardware, software, or a combination of the two.